PCB Impedance Control: Fundamental Principles

Introduction: Why Impedance Control?

As signal speeds increase in modern electronic systems, copper traces on a PCB can no longer be treated as simple conductors. The moment clock frequencies exceed the MHz range, every printed circuit trace begins to behave as a transmission line. This is where the concept of characteristic impedance becomes critical.

Impedance mismatch causes signal reflections, ringing, overshoot/undershoot, and timing skew. Particularly in high-speed protocols such as DDR memory interfaces, USB 3.x, PCIe, HDMI, and Ethernet, failure in impedance control directly leads to system errors.

What Is Characteristic Impedance?

The characteristic impedance (Z0) of a transmission line depends on the ratio of per-unit-length inductance (L) and capacitance (C):

Z0 = sqrt(L / C)

In the PCB context, this value depends on the following parameters:

• Trace width: Wider traces produce lower impedance.
• Dielectric height: The distance between the trace and the reference plane.
• Copper weight: Typically 1 oz (35 um) or 0.5 oz (17.5 um).
• Dielectric constant (Dk/Er): For FR-4, typically 4.2-4.6. For high-speed applications, Megtron 6 (Dk ~3.7) or Rogers materials are preferred.
• Solder mask: Solder mask over the trace changes the effective dielectric constant; this effect is often neglected but should be considered at >10 Gbps.

Common Impedance Structures

Microstrip (Outer Layer)

Microstrip is a structure where the signal trace is on the outer surface of the PCB with the reference plane immediately below. IPC-2141 is the reference standard for calculations. For a typical 50-ohm microstrip:

• FR-4 (Er = 4.3), dielectric thickness 0.2 mm
• Trace width: approximately 0.30-0.35 mm (1 oz copper)

Advantages: Easy to manufacture, lower cost. Disadvantages: Susceptible to EMI radiation, higher crosstalk risk.

Stripline (Inner Layer)

In the stripline structure, the signal trace is sandwiched between two reference planes. This structure naturally provides a shielded environment.

• With the same parameters, stripline requires narrower traces compared to microstrip (because two reference planes increase capacitance).
• Typical 50-ohm stripline: trace width ~0.15-0.20 mm (dielectric 0.2 mm on each side).

Advantages: Low EMI, better signal integrity. Disadvantages: Occupies inner layer space, reducing routing density.

Differential Pairs

Protocols like USB, HDMI, PCIe, and LVDS use differential signaling. Here, two traces run in parallel and the differential impedance (Zdiff) is controlled. Typical values:

Differential impedance is highly sensitive to the spacing between the two traces. As spacing increases, Zdiff increases; as spacing decreases, Zdiff drops. General rule: spacing = 1-3x trace width.

Stackup Design

In controlled impedance PCB design, the stackup is one of the most critical decisions. Example 6-layer stackup:

Layer 1 (TOP)     : Signal (microstrip)
Layer 2 (GND)     : Ground plane
Layer 3 (SIG)     : Signal (stripline)
Layer 4 (PWR)     : Power plane
Layer 5 (GND)     : Ground plane
Layer 6 (BOTTOM)  : Signal (microstrip)

Fundamental rules:

• Every signal layer must have an adjacent reference plane.
• High-speed signals should be routed on stripline layers.
• Power and ground planes should be placed close together; this provides decoupling capacitance.
• Via transitions break impedance continuity. Via stubs at >5 Gbps should be addressed with back-drilling or HDI technology.

Impedance Calculation Tools

While IPC-2141 formulas can be used for manual calculation, these tools are used in practice:

• Saturn PCB Design Toolkit (free): Microstrip/stripline/differential calculations.
• Polar Instruments Si9000: Industry standard; PCB manufacturers use this tool.
• Altium Designer built-in impedance profile manager.
• KiCad + online calculators: JLCPCB impedance calculator, EEWeb Microstrip Calculator.

Important: A tolerance of +/- 10% between calculated and manufactured values is normal. A TDR (Time Domain Reflectometry) measurement report should always be requested from the manufacturer and verified with test coupons.

Signal Integrity Problems and Solutions

Reflection

At every point of impedance mismatch, a portion of the signal energy is reflected back toward the source. The reflection coefficient:

rho = (ZL - Z0) / (ZL + Z0)

Solution: With series termination, source impedance + series resistor = Z0. Parallel termination can also be used but increases power consumption.

Crosstalk

Capacitive and inductive coupling occurs between adjacent traces. Mitigation methods:

• Trace spacing >= 3x dielectric height (3W rule).
• Reference plane continuity must be maintained.
• Guard traces can be used between sensitive signals.

Power Integrity

Impedance control is not only for signal traces but also for the power distribution network (PDN). The target PDN impedance must be sufficiently low across the frequency range where the IC operates. The placement, values, and via connections of decoupling capacitors are critical to achieving this target.

Manufacturing and Quality Control

When ordering controlled impedance PCBs, the following information must be provided to the manufacturer:

1. Stackup details
2. Target impedance values and tolerance (e.g., 50 ohms +/- 10%)
3. Which nets require controlled impedance
4. Dielectric material preference (FR-4, IS410, Megtron 6, Rogers, etc.)
5. Test coupon requirement and TDR report request

The manufacturer's raw material lot, press temperature, and duration directly affect impedance values. Therefore, requesting TDR measurement reports even in prototype production is best practice.

Conclusion

PCB impedance control is the cornerstone of high-speed system design. With proper stackup, appropriate material selection, careful trace design, and manufacturing verification, signal integrity issues can be largely prevented. During the design phase, impedance profiles should be verified with simulation tools (HyperLynx, Ansys HFSS, Keysight ADS), and post-manufacturing confirmation should be done with TDR measurements.