Preparing for EMC Tests: Practical Tips

Introduction: What Is EMC and Why Does It Matter?

Electromagnetic Compatibility (EMC) means that an electronic device neither emits unacceptable levels of electromagnetic noise to its environment (emission) nor is affected by electromagnetic noise from its surroundings (immunity).

CE marking is mandatory for the European market, TSE conformity certificate for Turkey, and FCC certification for the USA. A product that fails EMC tests cannot legally be placed on the market. But the issue goes beyond legal compliance: EMC problems cause field failures, data loss, and safety risks.

In this article, we provide a practical guide covering the entire process from EMC pre-compliance testing to official laboratory testing.

EMC Test Categories

1. Emission Tests

Measurement of the electromagnetic energy your device radiates to the environment:

Conducted Emission (CE)

• Noise transmitted to the mains through the power cable.
• Frequency range: 150 kHz - 30 MHz.
• Standard: EN 55032 (multimedia equipment), EN 55011 (industrial).
• Measurement: Using LISN (Line Impedance Stabilization Network).

Radiated Emission (RE)

• Electromagnetic waves radiated from the device into the air.
• Frequency range: 30 MHz - 6 GHz (depending on product class).
• Standard: EN 55032.
• Measurement: In a 3 m or 10 m semi-anechoic chamber.

2. Immunity Tests

Your device's resilience to external electromagnetic effects:

EMC Measures During the Design Phase

Solving EMC problems during the design phase rather than the testing phase is both cheaper and more effective. The following measures significantly increase the probability of passing EMC tests.

PCB Design

Ground Plane Continuity: The most critical rule is to ensure an uninterrupted ground plane. Splits in the ground plane increase the current loop area and raise both emission and noise susceptibility. There must be no discontinuity in the reference plane beneath the signal trace. Trace Routing Strategy:

• High-speed signals should be routed on inner layers (stripline).
• Clock signals should be kept as short as possible; long clock lines should be terminated with series resistors.
• Sensitive analog signals should be physically separated from digital signals.
• Slots should be added in large copper pours to reduce antenna effects.

Decoupling:

• Place 100 nF ceramic capacitors as close as possible to every IC's VCC/GND pins.
• Use 100 nF + 10 uF + 1 uF combinations for broadband decoupling.
• Capacitor vias should be as close as possible to IC pads.

Enclosure and Cabling

Metallic Enclosure: A metallic enclosure acts as a Faraday cage. However, its effectiveness depends on controlling apertures:

• Enclosure slots must be smaller than 1/20 of the wavelength at the frequency of concern.
• For 1 GHz, maximum slot: ~15 mm.
• Ventilation openings should be designed as many small holes (instead of one large opening).
• Conductive gaskets (EMI gaskets) should be used at enclosure seams.

Cable Entries:

• Use filters at every cable entry (EMI filter for power lines, ferrite cores for signal lines).
• Unshielded cables should be kept as short as possible.
• Cable shields must be grounded with a 360-degree connection to the enclosure; pigtail connections are unacceptable.

Power Supply Design

Switch-mode power supplies (SMPS) are the most common source of EMC issues:

• Input filter: Common-mode choke + X capacitor + Y capacitor combination.
• Snubber circuit: RC snubber on the switching element (MOSFET) suppresses ringing.
• Layout: Place the input filter close to the SMPS IC. Minimize the power loop area.
• Stitching vias between power and ground planes on PCB: One GND via every 5-10 mm.

Pre-Compliance Testing Process

Official laboratory tests are expensive and time-consuming (typically 3-5 days, 5,000-15,000 EUR). Pre-compliance testing to detect issues early saves significant costs.

Required Equipment

• Near-field probe set: Magnetic (H-field) and electric field (E-field) probes.
• Spectrum analyzer: 9 kHz - 3 GHz range; sufficient for pre-scanning even without a full EMI receiver.
• LISN: For conducted emission pre-testing.
• ESD simulator: IEC 61000-4-2 compliant (can be rented if not owned).

Pre-Test Step by Step

Step 1: Near-Field Scanning

Scan over the PCB with a near-field probe while the device is operating. High emission points are typically found around:

• SMPS inductor and MOSFET area
• Crystal oscillator
• High-speed ICs (FPGA, MCU, DDR)
• Long PCB traces or cables

Step 2: Conducted Emission Pre-Test

Measure power cable emissions through the LISN. Compare with EN 55032 Class B limits. If limits are exceeded:

• Strengthen the input filter (higher common-mode attenuation).
• Add clip-on ferrites to the power cable.
• Check SMPS switching frequency (is spread spectrum modulation active?).

Step 3: Radiated Emission Estimation

A semi-anechoic chamber is required for full radiated emission measurement. However, estimates can be made based on near-field results and experience. General rule: signals approaching the limit by 20 dB in near-field may cause limit violations in far-field.

Step 4: Functional Test State Documentation

Determine which modes the device will be tested in during official testing. Define the worst-case scenario:

• All ports connected (cable lengths and types specified)
• Under maximum processing load
• All communication interfaces active

Laboratory Selection and Test Process

Accredited Laboratory Selection

• In Turkey: TURKAK accredited laboratories (e.g., TUBITAK UME, SGS, Bureau Veritas, Intertek).
• In Europe: DAkkS, UKAS accredited laboratories.
• A2LA accreditation is valid for the US market (FCC).

Pre-Test Preparation Checklist

1. Product samples: At least 2 units, same configuration as serial production.
2. Technical documentation: Circuit schematic, PCB layout, BOM, user manual.
3. Test mode definition: Which modes will be tested (standby, active, max load).
4. Cable and accessory list: All connection cables, power adapter, antenna (if applicable).
5. Special test fixture: Must be prepared in advance if the device requires special mounting.
6. Software version: Record of the software version being tested.

During Testing

• Stay in communication with the test engineer at the laboratory.
• Don't panic at the first failure: most issues can be resolved on-site (adding ferrites, rerouting cables, adding filtering).
• Take photographs: Document every test configuration; reproducibility is critical.
• If you fail emission tests, improve to pass with a 6 dB margin (barely passing is risky; production variations may exceed the limit).

Common Mistakes and Solutions

Mistake 1: Ground Plane Splits

If a split occurs in the reference plane beneath a signal trace on a multilayer PCB, the current loop area increases and emission rises significantly.

Solution: At via transitions where the signal trace changes reference planes, add a ground via at the same point (return current via).

Mistake 2: Cable Shield Pigtail Connection

Grounding a shielded cable's shield with a single wire (pigtail) virtually eliminates the shield's effectiveness at high frequencies.

Solution: 360-degree shield connection (full contact with the connector's metallic shell).

Mistake 3: Post-Filter Coupling

If traces after the input EMI filter run in the same cable bundle or on adjacent traces with pre-filter lines, the filter is bypassed.

Solution: Physically separate filter input and output traces. On the PCB, filter components should be placed close to the input connector.

Mistake 4: Lack of ESD Protection

Every connector accessible to the user (USB, Ethernet, SD card, buttons) must have ESD protection diodes.

Solution: TVS diodes (e.g., USBLC6-2, PESD5V0S1BSF) on data lines, varistors or TVS on power lines. The protection element should be placed close to the connector, not the IC being protected.

Cost and Time Planning

Important: Include the test schedule early in the product development plan. The "design is done, now let's test" approach typically results in cost and time overruns. Ideally, pre-testing should be done at the prototype stage and official testing completed before serial production.

Conclusion

Preparing for EMC tests is an integral part of product design. With proper PCB design, effective filtering, appropriate enclosure design, and thorough pre-compliance testing, the probability of passing on the first attempt can be significantly increased. Starting with EMC in mind during the design phase is always more economical and effective than solving problems during testing.